This invention relates to Phase-locked loops (PLL""s), and more particularly to digitally-tuned dual PLL""s.
Accurate clocks are often used to synchronize the timing of operations and data transfers. A crystal oscillator can be used to generate a clock at a base frequency, which is then divided or multiplied to create one or more clocks with desired frequencies. External clock can be received and likewise divided or multiplied to produce internal clocks.
Clocks are typically generated from oscillator outputs using phase-locked loops (PLL""s). PLLs are one of the most widely use building blocks in digital systems today. See for example, U.S. Pat. No. 6,124,741 by Arcus, and assigned to Pericom Semiconductor Corp. of San Jose, Calif.
FIG. 1 illustrates a typical PLL. Phase detector 10 receives a reference-clock input from an external oscillator or clock source. The phase and frequency of the reference clock is compared to the phase and frequency of a feedback clock generated by voltage-controlled oscillator (VCO) 14. The feedback clock can be the output clock generated by the PLL, or a divided-down derivative of the output clock from VCO 14.
Phase detector 10 outputs up and down signals UP, DN when the phase or frequency of one input does not match the phase or frequency of the other input. These up and down signals cause charge pump 12 to add or remove charge from filter capacitor 19, which integrates the charge. As charge is added or removed from filter capacitor 19, the voltage input to VCO 14 is increased or decreased. VCO 14 responds by increasing or decreasing the frequency of the output clock. The feedback clock to phase detector 10 is likewise changed by VCO 14.
As charge pump 12 adds or removes charge from filter capacitor 19, altering control voltage VCTL input to VCO 14, the phase and frequency of the feedback clock are adjusted until the reference clock is matched. Then phase detector 10 stops generating up and down signals to charge pump 12, until charge leaks off filter capacitor 19 or the reference clock changes.
Often the reference or input frequency is not exactly the same as the desired output frequency. The reference frequency may be divided or multiplied to obtain the output frequency, but the desired output frequency may still not be a multiple or divisor of the reference frequency. For example, the desired frequency may be an abstract frequency completely unrelated to the reference frequency. In the past, the system designer chose the reference frequency to be an exact multiple or divisor of the desired frequency.
Various PLL""s with multiple loops have been developed. See U.S. Pat. No. 5,943,382 by Li et al., U.S. Pat. No. 5,393,250 by Imaizumi et al., U.S. Pat. No. 5,075,639 by Taya, and U.S. Pat. No. 5,317,284 by Yang. While useful, a dual-loop PLL that outputs a clock with a finely-adjustable frequency is desired.
A widely used building-block is the digital-to-analog converter (DAC). DAC""s have been used at interfaces between digital and analog parts of a system, such as for converting digital codes to analog voltages. A variety of real-world analog devices such as audio speakers, motors, video displays, and phone lines can then be driven. While useful in such applications, DAC""s are not generally used for generating clock signals. However, see U.S. Pat. No. 5,881,111 by Anzai, which uses a pair of D/A and A/D converters in a loop in a frequency sweep circuit. Also see U.S. Pat. No. 5,329,251 by Llewellyn, which teaches a DAC used with a multiple-PLL clock recovery circuit.
In some applications, it is desired to finely-tune the output frequency. Digital tuning of the output frequency is desired. It is desired to use a digital code word to select from a range of possible output frequencies. It is useful to digitally tune the output frequency without requiring any change to the reference frequency. Digital adjustment of the output frequency is desirable. A PLL that uses a fixed reference frequency input, but that can generate a range of finely-tuned output frequencies, is desirable.